The present invention relates generally to a semiconductor memory device and more particularly to a semiconductor memory device having a redundant circuit for replacing defects by using programmable elements for storing a defect address value.
As semiconductor devices are made with finer geometries, the memory capacity of a semiconductor memory device, such as a dynamic random access memory (DRAM), becomes increasingly large. As the size of device structures is decreased, such as in the memory array region, manufacturing defects are increased, thereby decreasing the product yield and increasing manufacturing costs. For this reason, it is essential to incorporate redundant circuits to replace one or more defective memory cells in a mass memory. A redundant circuit for a semiconductor memory device includes a redundant row or a redundant column, which can correspond to a normal row or normal column in the memory cell array. The redundant circuit also includes a structure for detecting an address match between the applied address and a stored defective address. When an address match is indicated the corresponding normal row or normal column is replaced with a redundant row or a redundant column. In this way, a semiconductor memory device having a defect can still be used as a good device and yield can be increased.
A description will now be given of conventional approaches for detecting whether or not the applied address, such as an external address, coincides with the stored defective address.
Referring now to FIG. 9(a), a conventional defect detecting circuit is set forth in a block schematic diagram and given the general reference character 700.
The conventional defect detecting circuit 700 detects an address match between the applied address (A0 to An) and a stored defective address and generates a coincidence detection signal RE.
Conventional defect detecting circuit 700 includes a coincidence detecting circuit 700A and an address transition detecting circuit 700B. Coincidence detecting circuit 700A detects the coincidence of an externally input address (A0 to An) with a stored defective address. Coincidence detecting circuit 700A is initialized in response to a reset signal xcfx86r every time a new externally input address is received. Address transition detecting circuit 700B detects a change in the externally input address (A0 to An) to generate the reset signal xcfx86r.
Referring now to FIG. 9(b) coincidence detecting circuit 700A is set forth in a circuit schematic diagram.
Coincidence detecting circuit 700A includes a p-type field effect transistor TP700 having a source connected to VDD, a drain connected to internal lode ND, and a gate connected to receive reset signal xcfx86r. P-type field effect transistor TP700 forms a precharge path between internal node ND and VDD. For each address received, there are two discharge paths between internal node ND and VSS. For address A0, a first discharge path is formed by n-type field effect transistor TN0T and fuse F0T and a second discharge path is formed by n-type field effect transistor TN0N and fuse F0N. N-type field effect transistor TN0T has a source connected to VSS, a drain connected to a first fuse terminal, and a gate connected to receive true address A0T. Fuse F0T has a second fuse terminal connected to internal node ND. N-type field effect transistor TN0N has a source connected to VSS, a drain connected to a first fuse terminal, and a gate connected to receive complementary address A0N. Fuse F0N has a second fuse terminal connected to internal node ND. Similarly, N-type field effect transistors (TN1T-TN1N to TNnT-TNnN) and fuses (F1T-F1N to FnT-FnN), respectively, are configured to provide two discharge paths between internal node ND and VSS for each address (A1 to An). However, only one of each of the two discharge paths is active at any time based on whether the corresponding address has a logic one or logic zero value. For example, if address A0 is high, true address A0T is high and n-type field effect transistor TN0T is turned on and the discharge path formed by n-type field effect transistor TN0T and fuse F0T is turned on. Also, complementary address A0N is low and n-type field effect transistor TN0N is turned off, and the discharge path formed by n-type field effect transistor TN0N and fuse F0T is turned off. However, if address A0 is low, complementary address A0T is high and n-type field effect transistor TN0N is turned on. Also, true address A0T is low and n-type field effect transistor TN0T is turned off and the discharge path formed by n-type field effect transistor TN0T and fuse F0T is turned off. Discharge paths that receive true and complementary address bits (A1T-A1N to AnT-AnN) are similarly configured.
Fuses that are programmed to indicate either a logic one or a logic zero for each address (A0 to An) is programmed for the stored defective address. For example, if the stored defective address has an address A0 that is a logic one, fuse F0T is blown or opened. Thus, when received address A0 is high, true address TN0T is high. However, even though n-type field effect transistor TN0T is turned on, fuse F0T prevents the discharge path formed by n-type field effect transistor TN0T and fuse F0T from being enabled. Likewise, if the stored defective address has an address A0 that is a logic zero, fuse F0N is blown or opened. Thus, when received address A0 is low, complementary address A0T is high. However, even though n-type field effect transistor A0N is turned on, fuse F0N prevents the discharge path formed by n-type field effect transistor TN0N and fuse F0N from being enabled. Other stored addresses are similarly programmed so that when there is a match between the applied address (A0 to An) and the stored address, all discharge paths are disabled and internal node ND remains high.
Buffer BF700 receives internal node ND and provides a coincidence detection signal RE.
The operation of the first conventional example illustrated in FIG. 9 will now be described.
First, a defect address is determined by a probe test. Fuses (F0T-F0N to FnT-FnN) are selectively cut or blown in accordance with the defect address to provide a stored defect address in the coincidence detecting circuit 700A. For example, when the least significant bit of the defect address is a logic one, fuse F0T, of the pair of fuses (F0T and F0N) that correspond to external address A0, is blown or cut. In this way, fuse F0T that forms the discharge path when the true address A0T is high is cut and fuse F0N that forms the discharge path when the complementary address A0T is high is left intact. Respective fuse pairs (F1T-F1N to FnT-FnN) are programmed in accordance with other logic values of the defect address.
As described above, the stored defect address is programmed in the coincidence detecting circuit 700A. During operation, the stored defect address is compared with the receive address (A0 to An) every time the received address (A0 to An) changes value. In other words, for example, if the external address A0 changes from a logic zero to a logic one, address transition detecting circuit 700B detects the change (transition) and outputs a low level pulse as the reset signal xcfx86r. Upon receiving the reset signal xcfx86r, the p-type field effect transistor TP700 in coincidence detecting circuit 700A is temporarily turned on to charge (precharge) the parasitic capacitance of the internal node ND to a high level.
When the address A0 changes to a logic one, true address A0T becomes high and n-type field effect transistor TN0T is turned on. However, because fuse F0T is in the cut state, the discharge path formed by n-type field effect transistor TN0T and fuse F0T does not conduct current. Because address A0 is low, complementary address A0T remains low and n-type field effect transistor TN0N is turned off. Because n-type field effect transistor TN0N is turned off, the discharge path formed by n-type field effect transistor TN0N and fuse F0N does not conduct current. Because both discharge paths remain turned off (and assuming other discharge paths corresponding to other addresses (Al to An) are off due to matches with the corresponding stored defect address), internal node ND remains at the high level and the received address (A0 to An) matches with the stored defect address. In response to a high internal node ND, buffer BF700 outputs a coincidence detection signal RE having a high level.
However, when the address A0 changes from a logic one to a logic zero, complementary address signal A0T becomes high. With complementary address signal A0T high, n-type field effect transistor TN0N turns on and internal node ND is discharged through the discharge path n-type field effect transistor TN0N and fuse F0N. Similarly, other discharge paths may be turned on when the applied address (A1 to An) does not match with the corresponding stored defect address.
In this way, when an applied address (A0 to An) does not match with the stored address, internal node ND becomes low and buffer BF700 outputs a coincidence detection signal RE having a low level. However, when an applied address (A0 to An) does match with the stored address, internal node ND remains high and buffer BF700 outputs a coincidence detection signal RE having a high level.
In the first conventional example illustrated in FIG. 9, reset signal xcfx86r is a low going pulse and p-type field effect transistor TP700 is only turned on during the pulse low period. In this way, there is no static current flowing through the fuses from VDD to VSS and current consumption of the conventional defect detecting circuit 700 can be reduced.
Referring now to FIG. 10(a), a second conventional defect detecting circuit is set forth in a circuit schematic diagram and given the general reference character 800.
Conventional defect detecting circuit 800 is configured to select the true address bit or complementary address bit on the basis of the program state of a corresponding fuse for each stored defective address bit. In FIG. 10(a), only circuitry corresponding to received address A0 is illustrated to avoid unduly cluttering the figure. Conventional defect detecting circuit 800 includes a fuse circuit 800A, a signal select circuit 800B, and a logical product circuit 800C. Fuse circuit 800A stores a defect address for address A0 and provides a defect address value FA0 to signal select circuit 800B. Signal select circuit 800B receives applied address A0 and provides either a true address A0T or a complementary address A0N to logical product circuit 800C in response to the logic level of defect address value FA0. A fuse circuit 800A and a signal select circuit 800B is provided corresponding to each remaining address (A1 to An). Logical product circuit 800C receives the true or complementary address (A0T/A0N to AnT/AnN) from respective signal select circuits 800B and provides a coincidence detection signal RE in response thereto.
Signal select circuit 800B includes n-type field effect transistors (801B and 802B) and inverters (803B and 804B). N-type field effect transistor 801B has a source connected to receive applied address A0, a drain connected to logical product circuit 800C and a gate connected to receive defect address value FA0. N-type field effect transistor 802B has a source connected to receive applied address A0 through inverter 803B, a drain commonly connected to the drain of n-type field effect transistor 801B, and a gate connected to receive defect address value FA0 through inverter 804B.
Referring now to FIG. 10(b), fuse circuit 800A is set forth in a circuit schematic diagram.
Fuse circuit 800A includes a fuse 801A, resistors (802A and 803A), an inverter 804A, and a n-type field effect transistor 805A. Fuse 801A has one terminal connected to VDD and another terminal connected to a connection node. Resistor 802A has one terminal connected to VSS and another terminal connected to a connection node. Inverter 804A has an input connected to connection node and an output connected to provide defect address value FA0. N-type field effect transistor 805A has a source connected to VSS, a drain connected to the connection node and a gate connected to receive defect address value FA0. Resistor 803A has one terminal connected to VDD and another terminal connected to defect address value FA0.
When fuse 801A is not cut (intact), the input of inverter 804A is forced high through fuse 801A. With a high input, inverter 804A provides a defect address value FA0 having a low level. In this case, stored address bit in fuse circuit 800A corresponding to address A0 has a logic zero.
When fuse 801A is cut or blown, the input of inverter 804A is forced low through resistor 802A. With a low input, inverter 804A provides a defect address value FA0 having a high level. At the same time, the defect address value FA0 is pulled up by resistor 803A. When defect address value FA0 rises a threshold voltage of n-type field effect transistor 805A above VSS, n-type field effect transistor 805A is turned on to latch a logic low at the input of inverter 804A. In this case, stored address bit in fuse circuit 800A corresponding to address A0 has a logic one and defect address value FA0 has a high level.
In this way, fuse circuit 800A is configured to store and output defect address value FA0 having a logical value (one or zero) in accordance with the state of fuse 801A (intact or cut).
The operation of conventional defect detecting circuit 800 illustrated in FIG. 10 will now be described.
Defect address detecting circuit 800 provides a coincidence detection signal RE having a high level only when all of the input signals to the logical product circuit 800C are at a high level and thereby detects that the defect address and the applied address (A0 to An) coincide or match with each other. Therefore, when the applied address (A0 to An) has the same logical values as the stored defect address, the defect address values (FA0 to FAn) from respective fuse circuits 800A are provided in combination with applied address (A0 to An) to respective signal select circuits 800B so that input signals of the logical product circuit 800C become high. Thus, the select state is determined in accordance with the stored defect address programmed in the fuse circuit 800A matching the applied address (A0 to An).
When a logic zero is programmed in the fuse circuit 800A (fuse 801A intact), defect address value FA0 is low. With defect address value FA0 is low, n-type field effect transistor 801B is turned off. Inverter 804B provides a logic one (high value) to the gate of n-type field effect transistor 802B. Thus, n-type field effect transistor 802B is turned on. With n-type field effect transistor 801B turned off and n-type field effect transistor 802B turned on, signal select circuit 800B provides the complementary address A0T from the output of inverter 803B to the input of logical product circuit 800C. In this way, when a logic zero is programmed in the fuse circuit 800A, the signal select circuit 800B outputs a high level to the logical product circuit 800C only the applied address A0 is a logic zero.
When a logic one is programmed in the fuse circuit 800A (fuse 801A blown or cut), defect address value FA0 is high. With defect address value FA0 is high, n-type field effect transistor 801B is turned on. Inverter 804B provides a logic zero (low value) to the gate of n-type field effect transistor 802B. Thus, n-type field effect transistor 802B is turned off. With n-type field effect transistor 801B turned on and n-type field effect transistor 802B turned off, signal select circuit 800B provides the true address A0T to the input of logical product circuit 800C. In this way, when a logic one is programmed in the fuse circuit 800A, the signal select circuit 800B outputs a high level to the logical product circuit 800C only the applied address A0 is a logic one.
Other applied addresses (A1 to An) include a fuse circuit 800A and signal select circuit 800B that operate in the same manner as described above.
Accordingly, only when the combination of logic values of the applied address (A0 to An) coincides or matches with the combination of logic values of the stored defect address, all the inputs to logical product circuit 800C become high and coincidence detection signal RE having a logic high is output. In this way, it is possible to detect an address location that has been replaced with redundant circuits on the basis of the coincidence detection signal RE.
In the second conventional example as illustrated in FIG. 10, an operation for charging the internal node in accordance with the reset signal xcfx86r is not needed. Thus, the operating speed of the second conventional example as illustrated in FIG. 10 may be improved over the first conventional example as illustrated in FIG. 9.
Referring now to FIG. 11, a third conventional example is set forth illustrating a fuse circuit for indicating whether or not a redundant circuit is being used. The fuse circuit is given the general reference character 1100. Fuse circuit 1100 is disclosed in Japanese Patent Application Laid-open No. Hei 5-89696.
Fuse circuit 1100 includes fuses (FA and FB) connected in series between a power supply and ground. Either fuse FA or fuse FB is cut or blown in accordance with whether or not a particular redundant circuit is being used. In this way, the potential V1 at a connection node between fuse FA and fuse FB indicates the use of a redundant circuit.
In this way, potential V1 is determined by providing a power supply potential to the connection node through the intact fuse (FA or FB). Thus, the use of redundancy can be determined immediately after the power supply turns on without the risk of malfunction by providing power-up setting circuitry.
Referring now to FIG. 12, a fourth conventional example is set forth illustrating an address program circuit designated by the general reference character 900.
Address program circuit 900 is used to program a defect address and includes pairs of fuses (901 and 902) corresponding to the number of address bits used to identify redundant circuit replacement. Fuses (901 and 902) operate as a unit pair and one of the unit pair of fuses (901 or 902) is cut corresponding to the value of the address bit corresponding to the defective circuit that is being replaced with a redundant circuit.
When stored defect address AX0S is programmed to have a logic zero, fuse 901, of the pair of fuses (901 and 902), is cut. As a result, the potential of the connection node between fuses (901 and 902) is fixed to the ground potential to provide a stored defect address AX0S having a logic zero.
Alternatively, when stored defect address AX0S is programmed to have a logic one, fuse 902, of the pair of fuses (901 and 902), is cut. As a result, the potential of the connection node between fuses (901 and 902) is fixed to the power supply potential (through p-type field effect transistor 903) to provide a stored defect address AX0S having a logic one.
The operation of the address program circuit 900 will now be briefly described. P-type field effect transistor 903 is turned off during the reset operation. During this time, current consumption may be eliminated by preventing current from flowing through fuses (901 and 902). However, in normal operation, p-type field effect transistor 903 is turned on. As a result, the programmed logic values (zero or one) is output as stored defect addresses (AX0S to AX7S) in accordance with the states of fuses (901 and 902).
According to the fourth conventional example illustrated in FIG. 12, the logic values of stored defect addresses (AX0S to AX7S) are simultaneously set by turning p-type field effect transistor 903 on to provide power. In this way, there may be no dependence in access time based on a difference in the stored defect address.
Note that, according to the first conventional example illustrated in FIG. 9, it is necessary that a change in the applied addresses (A0 to An) is detected by the address transition detecting circuit 700B to generate the reset signal xcfx86r in order to charge the internal node ND of the coincidence detecting circuit 700A before comparing the applied addresses (A0 to An) with the stored defect address. Thus, a time delay may be required until a valid coincidence detection signal RE is generated. This can adversely affect the operating speed of the redundant circuit.
According to the second conventional example illustrated in FIG. 10, when fuse 801A of fuse circuit 800 is not cut, a current continuously flows between the power supply and ground through fuse 801A and resistor 802A. Also, because in this state inverter 804A outputs a low level, current continuously flows between the power supply and ground through resistor 803A and inverter 804A. For this reason, current consumption in the redundant circuit increases which may have adverse affects on standby and operating currents.
Additionally, according to the third conventional example illustrated in FIG. 11, when circuitry is tested to determine the necessity of using the redundant circuitry, both fuses (FA and FB) are in the intact state. During this time, the power supply and ground may be short-circuited through the fuses (FA and FB) thereby producing excessive current. This may cause fluctuations in the power supply level during the test period and can adversely affect the integrity of the test for defects. Japanese Patent Application Laid-open No. Hei 5-89696 also discloses an example in which a pad electrode for supplying a power supply to the fuses is disposed so that the power supply connection (pad electrode) may be made floating during the defect test. However, according to this example, the pad electrode needs to be bonded to an external terminal after the defect test has been performed. Thus, it is necessary to provide a pad electrode that satisfies the same design standard as that of a normal pad electrode. This can adversely affect the chip layout.
According to the fourth conventional example illustrated in FIG. 12, when circuitry is tested to determine the necessity of using the redundant circuitry, both fuses (901 and 902) are also in the intact state. Thus, when p-type field effect transistor 903 is turned on, an excessive current may flow through the fuses. This may cause fluctuations in the power supply level during the test period and can adversely affect the integrity of the test for defects.
In view of the above discussion, it would be desirable to provide a semiconductor memory device that may be capable of replacing defective circuitry with redundant circuits having low current consumption and high speeds. It would also be desirable to provide a semiconductor memory device that may have a defect test without allowing excessive current to occur which may adversely affect the integrity of the defect test.
According to the present embodiments, a semiconductor memory device includes a memory cell array and redundant memory cells. A stored defect address may be programmed in a defect address storing circuit corresponding with a defective address in the memory cell array. A controllable impedance device may be selectively turned off to reduce a current passing through intact fuses. The controllable impedance device may be turned off in response to a potential applied to a pad electrode, a predetermined combination of control signals, or a reset signal generated by a power on reset circuit. In this way, current may be reduced when the defect address storing circuit does not have a stored defective address. Also, current may be reduced during the semiconductor device characterization so that characterization results may be improved.
According to one aspect of the embodiments, a semiconductor memory device may include a defect address memory circuit that may be programmable to store a defect address corresponding to an address location of at least one normal memory cell in a memory cell array that is replaced with at least one redundant memory cell when a received address matches the defective address. The defect memory circuit may include first and second fuses electrically connected in series and coupled between a first supply potential and a second supply potential. One of the first and second fuses may be cut in accordance with a logical value of a bit of the defect address when the at least one normal memory cell is replaced with at least one redundant memory cell. A current cut off circuit may essentially cut off a current that passes through the first and second fuses during a characterization of the semiconductor memory device.
According to another aspect of the embodiments, the current cut off circuit may essentially cut off the current that passes through the first and second fuses when the defect memory circuit does not store the defect address.
According to another aspect of the embodiments, the current cut off circuit may include first and second field effect transistors having current paths coupled in series with the first and second fuses. A pad electrode may be coupled to a control gate of the first field effect transistor. A load device may be coupled between the first supply potential and the pad electrode. A fuse circuit may be coupled to a control gate of the second field effect transistor to determine a conductive state of the second field effect transistor in accordance with whether the defect memory circuit stores the defect address.
According to another aspect of the embodiments, the current cut off circuit may include a field effect transistor having a current path coupled in series with the first and second fuses. A flip-flop circuit may be coupled to a control gate of the field effect transistor.
According to another aspect of the embodiments, the current cut off circuit further includes a mode entry circuit that may detect a current cutoff mode to set the flip-flop in a state where the field effect transistor is turned off.
According to another aspect of the embodiments, the current cutoff circuit may include a programmable device to prevent the test mode entry circuit from setting the state of the flip-flop.
According to another aspect of the embodiments, upon power-up, the flip-flop may be set in a state where the field effect transistor is turned on.
According to another aspect of the embodiments, the current cut off circuit may include a reset circuit that detects a power up operation and may provide a reset signal to set the state of the flip-flop.
According to another aspect of the embodiments, a semiconductor memory device may include a defect address storing circuit programmable to store a defect address corresponding to an address location of at least one normal memory cell in a memory cell array that is replaced with at least one redundant memory cell. The defect address storing circuit may include a plurality of programmable element pairs. Each programmable element pair may include first and second programmable elements electrically connected in series and coupled between a first supply potential and an internal supply potential node. One of the first and second programmable elements may be programmed to be in a non-conductive state in accordance with a logical value of a corresponding bit of the defect address when the at least one normal memory cell is replaced with at least one redundant memory cell. A current cut off circuit may be coupled to the internal supply potential node and may essentially cut off a current that passes through the plurality of programmable element pairs during a characterization of the semiconductor memory device.
According to another aspect of the embodiments, the current cut off circuit may include a first field effect transistor coupled between the internal supply potential node and a second supply potential.
According to another aspect of the embodiments, the current cut off circuit may include a probe pad coupled to a control gate of the first field effect transistor.
According to another aspect of the embodiments, the current cut off circuit may include a mode circuit for detecting a characterization entry mode and coupled to provide a control signal to a control gate of the first field effect transistor.
According to another aspect of the embodiments, the characterization of the semiconductor memory device may be performed before the defect address is stored.
According to another aspect of the embodiments, a plurality of defect address storing circuit may be coupled to the current cut off circuit.
According to another aspect of the embodiments, in a normal mode of operation, the current cut off circuit may cut off the current that passes through the plurality of programmable element pairs for each of the plurality of defect address storing circuits that do not store a corresponding defect address. In the normal mode of operation, the current cut off circuit does not cut off the current that passes through the plurality of programmable element pairs for each of the plurality of defect address storing circuits that do store a corresponding defect address.
According to another aspect of the embodiments, a semiconductor memory device may include a defect address storing circuit may be programmable to store a defect address corresponding to an address location of at least one normal memory cell in a memory cell array that is replaced with at least one redundant memory cell. The defect address storing circuit may include a plurality of programmable element pairs. Each programmable element pair may include first and second programmable elements electrically connected in series and coupled between a first supply potential and an internal supply potential node. One of the first and second programmable elements may be programmed to be in a non-conductive state in accordance with a logical value of a corresponding bit of the defect address when the at least one normal memory cell is replaced with at least one redundant memory cell. A current cut off circuit may include a cut off circuit current path coupled between the internal supply potential node and a second supply potential and may essentially cut off the cut off circuit current path during a characterization of the semiconductor memory device.
According to another aspect of the embodiments, the cutoff circuit may include a third programmable element that is programmed according to whether the at least one normal memory cell is replaced with at least one redundant memory cell. The cut off circuit current path may be cut off when the third programmable element indicates that the at least one normal memory cell is not replaced with at least one redundant memory cell.
According to another aspect of the embodiments, the third programmable element may form a third programmable current path coupled between the first supply potential and the second supply potential. The cut off circuit may essentially cut off the third programmable current path during the characterization of the semiconductor memory device.
According to another aspect of the embodiments, the cut off circuit may include a probe pad that receives an externally applied potential during the characterization of the semiconductor memory device.
According to another aspect of the embodiments, the characterization of the semiconductor memory device may occur before a packaging step and before the programmable elements are selectively programmed.